1. Field of the Invention
The present invention relates to an apparatus for testing an electrical device, and more particularly, to an apparatus for testing an unpackaged, or bare, microchip.
2. Description of the Related Art
A need for more compact electronic devices has accelerated development of multi-chip modules (MCM's) which contain multiple semiconductor chips in a single package. However, the successful introduction of multi-chip modules to a commercial market requires a technology for producing known good dies (KGD's), i.e., bare chips that are as reliable as packaged chips. Therefore, there is a need in the industry for technologies that can test bare chips, both physical and electrical reliability tests, such as burn-in tests and electrical performance tests, in a reliable and cost-effective manner.
Two types of bare chip testing methods are available. One is a wafer-level test, and the other is a die-level test. In general, the wafer-level test has several technical difficulties associated with it. For example, a probe card having probes at a sufficiently fine pitch is difficult to fabricate. A conventional probe card often causes contact failures due to a slight bending of the probes. Further, the trend in the industry is toward larger wafers, with more chips per wafer and a higher degree of integration of circuitry into the chips, which exacerbates the problem.
In contrast, the die-level test is performed after the wafer is sawn into individual dies, or chips. A typical die-level test employs a carrier to mount and carry a bare, or unpackaged, chip during testing. The chip undergoes all the same reliability and electrical tests as a packaged chip while contained in the test carrier. For example, the carrier containing the bare chip is inserted into a test socket for an electrical performance test of the chip. After all the tests are completed, the bare chips are unloaded from the carriers, and the chips that passed the tests are designated as known good dies.
A typical carrier for testing bare chips is described in U.S. Pat. Nos. 5,543,725 and 5,656,945, which are both hereby incorporated by reference in their entireties. In U.S. Pat. No. 5,543,725, a carrier is described which has a cavity to receive a bare chip, and a "head" to establish a good contact between the bare chip and the carrier. In U.S. Pat. No. 5,656,945, a carrier is disclosed which has the shape of a commercial chip package, and a head to press a bare chip into the carrier so as to ensure a good electrical connection between the chip and contact terminals of the carrier. In the test methods using the carriers described in the above references, the loading/unloading of the bare chip must be carried out manually because the loading/unloading cannot be adapted to existing automated chip handling equipment.